An integrated inductor capable of operating at gigaHertz (109 Hz) frequencies is a critical element in, e.g., oscillators, filters, and wide-band low-noise amplifiers (LNAs). The main applications are radio-frequency (RF) communication and high-speed data processing ICs, such as those in cellular phones, wireless network cards, and broadband transceivers.
Integrated inductors may be classified as passive or active. Most passive integrated inductors are implemented by metal wires in spiral form, hence the name “spiral inductors.” Other passive integrated inductors employ a piece of bondwire or micromachined conductor structures. Active integrated inductors, on the other hand, are implemented with electronic circuits that employ transistors and capacitors to achieve an inductive input impedance. Active inductors have been gaining increasing attention because, although noisier, they occupy a much smaller semiconductor die area (as little as 2–10% of that of passive inductors), can be designed to have a larger inductance values, high quality factors (Q), and are electronically tunable.
There are two fundamental approaches to realizing an active inductor using only capacitors and active gain elements. One is an operational-amplifier (opamp) method, which can be used to design active inductors operating at moderate frequencies (up to about 100 MHz), because of the limited bandwidth and excessive phase shift of the opamps. FIG. 1A shows the other approach that employs a gyrator 10; which is the method used by almost all active inductors operating at gigaHertz (gHz) frequencies.
Gyrator 10 typically includes two transconductors 12 and 14 (voltage-to-current converters) connected in a negative feedback loop as shown in FIG. 1A. Each of transconductors 12 and 14, (gm1 and gm2), provides an output current proportional to the difference between the input voltages of transconductors 12 and 14, Iout=gm(Vin+−Vin−). The input impedance of gyrator 10 acts as a lossless inductor if both gm1 and gm2 are ideal:
                              Z          in                =                              s            ⁢                                                  ⁢                                          C                L                                                              g                  m1                                ⁢                                  g                  m2                                                              =                      sL            eq                                              (        1        )            
In real circuit implementations, both gm1 and gm2 have non-zero output conductances, go1, go2, and parasitic input and output capacitances. go1 and go2 will make the active inductor lossy and reduce the quality factor, Q. Some of the parasitic capacitances can be merged with (added to) CL, increasing the equivalent inductance Leq, while other capacitances will appear at the input terminal as C1, making the active inductor a resonator with a resonance frequency as represented by Eq. 2.
                              f          R                =                              1                          2              ⁢                                                          ⁢              π              ⁢                                                                    L                    eq                                    ⁢                                      C                    1                                                                                =                                    1                              2                ⁢                                                                  ⁢                π                                      ⁢                                                                                g                    m1                                    ⁢                                      g                    m2                                                                                        C                    L                                    ⁢                                      C                    1                                                                                                          (        2        )            
FIG. 1B shows the equivalent circuit of gyrator 10, where Rp represents an equivalent loss resistor, combining all the losses in gyrator 10. Below fR, the input impedance Zin is inductive; above fR, Zin is capacitive; at resonance, f=fR, Zin is resistive (Zin=Rp). There are typically two ways of applying an active inductor in RF circuit designs: as an inductor, when the application frequency f is less than fR, f<fR, and as a resonator, when f is around fR. The useable frequency range of the active inductor is, therefore, from near dc to fR. To operate the inductor at a frequency f in the gigaHertz range, fR needs to be higher than f, fR>f. To maximize fR, according to Eq. 2, gmi can be increased at the cost of increased power consumption and/or CL and C1 can be reduced to only the unavoidable parasitic capacitors, such as the gate-source capacitance (Cgs), the drain-diffusion capacitance (Cjd), and interconnect capacitances. The multiple-transistor transconductors with linearization employed in transconductor-capacitor (Gm-C) filters can not generally be used here, because their internal nodes generate parasitic poles, which increase the phase shift of the transconductors and severely reduce their useable frequency range. Therefore, transconductors with single or minimum-count transistors should be employed.
Prior integrated active inductors and their applications have been implemented in various IC fabrication technologies [1–16], such as Complementary Metal Oxide Semiconductor (CMOS), Bipolar, and Gallium-Arsenide (GaAs). CMOS is the preferred technology because of its low cost and compatibility with digital circuits. Modern submicron CMOS technology having a minimum transistor length L less than 1 μm brings quite a few challenges to active inductor designers. Among them: the transistors are intrinsically very lossy because of the short-channel effect, the supply voltage is low (≦1.8 V), the threshold voltages (VTs) are relatively high (0.5–0.7 V), and metal-insulator-metal (MiM) capacitors are not available in standard digital CMOS technologies.
Prior workers have employed various methods for constructing active inductors. Representative prior art references are discussed briefly below. Almost all gigaHertz active inductors are built on the principle of gyration, using transconductors with only single or minimum-count transistors. However, subject to the constraints of dc biasing and device characteristics, prior methods for constructing CMOS active inductors are very limited.
FIG. 2A shows a regulated cascode structure 20 that is employed by a large proportion of prior active inductor implementations [1–8]. FIG. 2B shows the small-signal equivalent circuit of cascode structure 20 with components defined asC1=Cgs2+Cjs1,C2=Cjd,IB+Cjd2+CL,g1=gds1,g2=gds2+gds,IBwhere
Cgs1, Cgs2 are the gate-source capacitances of transistors M1 and M2, respectively;
Cjs1 is the source diffusion capacitance of M1;
Cjd2, Cjd,IB are the drain diffusion capacitances of M2 and MIB, respectively;
CL is the load capacitor (if it exists); and
gds1, gds2, gds,IB are the drain-source conductances of M1, M2, and MIB, respectively.
The input impedance Zin of regulated cascode circuit 20 is
                                          Z            in                    ⁡                      (            s            )                          =                                            V              1                                      I              1                                =                                                                      s                  ⁡                                      (                                                                  C                        2                                            +                                              C                        gs1                                                              )                                                  +                                  g                  2                                                            D                ⁡                                  (                  s                  )                                                      =                          1                                                Y                  in                                ⁡                                  (                  s                  )                                                                                        (                  3          ⁢          a                )            withD(s)=s2[C1(C2+Cgs1)+C2Cgs1]+s[(gm1+g1)(C2+Cgs1)+(C1+Cgs1)g2+Cgs1(gm2−gm1)]+gm1gm2+(gm1+g1)g2  (3b)
Zin is resonant and is equivalent to that of the R-L-C parallel circuit shown in FIG. 2C:
                              Y          in                =                              sC            p                    +                      g            p                    +                      1                                          sL                eq                            +                              r                loss                                                                        (                  4          ⁢          a                )            with, approximately,
                    C        p            =                        C          1                +                                            C              2                        ⁢                          C              gs1                                                          C              2                        +                          C              gs1                                            ,                  ⁢                  g        p            =                        g          1                +                  g          m1                +                                                                              C                  gs1                                ⁡                                  (                                                            C                      gs1                                        +                                          C                      2                                                        )                                            ⁢                              (                                                      g                    m2                                    -                                      g                    m1                                                  )                                      +                                          C                gs1                2                            ⁢                              g                2                                                                        (                                                C                  2                                +                                  C                  gs1                                            )                        2                                          L      ≈                        (                                    C              2                        +                          C              gs1                                )                          (                                    g              m1                        ⁢                          g              m2                                )                      ,                  r        loss            ≈                        g          2                          (                                    g              m1                        ⁢                          g              m2                                )                    
The approximations are made assuming that g1≈g2<<|s(C2+Cgs1)|, gm1≈gm2. Regulated cascode circuit 20 is, however, an intrinsically low-Q circuit, because the input resistance at the source of M1 at Node 1 (FIG. 2A) is 1/gm1, which has a very low value. M1 serves as the non-inverting transconductor within the gyrator, but is not very efficient because of its common-drain arrangement.
To improve the Q, prior workers [2, 5–7] have employed an alternative cascode approach by adding cascode transistors on the drain of M2. However, this reduces the dynamic range of the circuit, and may be impossible to implement in low-voltage submicron technology. Other prior workers [3, 4, 8] have added negative resistors to compensate for the active-inductor loss, which reduces the maximum operating frequency and increases the noise.
Yet other workers [10] have described a simple CMOS active inductor structure employing feedback within the cascode circuit. However, this approach also has an intrinsically low-Q because a node between the two transistors is connected to the source of the top NMOS device and has very low impedance. A negative resistor is added to the circuit to enhance Q, but this undermines the frequency benefits that the simple structure may offer. Nonetheless, the regulated cascode circuit 20 active inductor and the circuit of[10] may be used to implement wide-band amplifiers and low-pass filters with potentially high performances, where high Q is not required.
Other prior workers [11–13] describe active inductor gyrator structures by connecting two differential transconductance amplifiers back to back. To enhance the Q, some workers use negative resistors [11], and other designers add series resistors in the feedback paths [12]. As a result, the final circuits are complex and the maximum operating frequency is reduced.
Karsilayan and Schaumann [14] describe a high-Q active inductor structure for implementing lowpass filters [15] and oscillators[16]. The signal path includes only three devices, two PMOS transistors and one NMOS transistor. Karsilayan's circuit overcomes most of the aforementioned disadvantages and operates up to 5 gHz in simulation (for 0.2 micron technology) and 4 gHz in experiment.
While working-around and solving some of the above-described problems, the prior active inductor structures using submicron CMOS technologies nevertheless exhibit several disadvantages:    a. The number of transistors employed in the prior circuits is typically large (four to nine or greater), and the operating frequency is limited to 1–2 gHz with submicron fabrication technologies, because the signal path contains too many nodes and hence multiple parasitic poles. The parasitic poles also make the impedance function more complex and the inductor harder to calibrate.    b. The signal path is a mixture of N-type MOS (NMOS) and P-type MOS (PMOS) transistors. The mobility of NMOS (μn) in submicron technologies is 4 to 5 times that of PMOS (μp), and the transconductance of MOS transistors (MOSFETs) is proportional to their mobility. Therefore, the maximum operating frequency of the active inductor is limited by the PMOS transistors.    c. Most prior structures have an intrinsically low Q, and must employ cascode structures or negative resistors to enhance Q to implement circuits, such as narrow-band bandpass filters. The negative resistor increases the noise and parasitic capacitance of the circuit. The cascode structure limits the dynamic range and is not compatible with low-voltage (≦1.8 V) operation. To reduce the circuit loss in these structures, the transistor lengths are usually 2–3 times the technology minimum, so that the high-speed advantage of submicron technology cannot be fully exploited. Generally, all three practices significantly reduce the maximum operating frequency.    d. Many prior designs employ costly modified CMOS technologies to derive components normally not available in standard digital CMOS technologies, such as MiM capacitors, or to enhance the characteristics of CMOS transistors, such as lowering VT.
What is still needed, therefore, is a active inductor structure that solves the above-described problems.